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a
32-Channel 14-Bit DAC with High-Speed 3-Wire Serial Interface AD5532HS*
GENERAL DESCRIPTION
FEATURES High Integration: 32-Channel DAC in 12 12 mm2 LFBGA Guaranteed Monotonic DSP-/Microcontroller-Compatible Serial Interface Channel Update Rate 1.1 MHz Output Impedance 0.5 Selectable Output Voltage 0 V to 5 V or -2.5 V to +2.5 V Asynchronous RESET Facility Temperature Range -40 C to +85 C APPLICATIONS Optical Networks Level Setting Instrumentation Automatic Test Equipment Industrial Control Systems Data Acquisition Low Cost I/O
The AD5532HS is a 32-channel voltage-output 14-bit DAC with a high-speed serial interface. The selected DAC register is written to via the 3-wire interface. The serial interface operates at clock rates up to 30 MHz and is compatible with DSP and microcontroller interface standards. The output voltage range is 0 V to 5 V or -2.5 V to +2.5 V and is determined by the offset voltage at the OFFS_IN pin. It is restricted to a range from VSS + 2 V to VDD - 2 V because of the headroom of the output amplifier. The device is operated with AVCC = 5 V 5%, DVCC = 2.7 V to 5.25 V, VSS = -4.75 V to -12 V and VDD = +4.75 V to +12 V and requires a stable 2.5 V reference on REF_IN.
PRODUCT HIGHLIGHTS
1. 32 14-bit DACs in one package, guaranteed monotonic. 2. The AD5532HS is available in a 74-ball LFBGA package with a body size of 12 mm by 12 mm.
FUNCTIONAL BLOCK DIAGRAM
DVCC AVCC REF_IN OFFS_IN VDD VSS
AD5532HS
DAC RESET DAC_GND AGND
14-BIT BUS
R R VOUT0 R R DAC R R VOUT30 R VOUT1
DGND DAC INTERFACE CONTROL LOGIC R DAC
VOUT31
SCLK
DIN
SYNC
*Protected by U.S. Patent No. 5,969,657; other patents pending.
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2001
AD5532HS-SPECIFICATIONS
(VDD = +4.75 V to +12 V, VSS = -4.75 V to -12 V; AVCC = 4.75 V to 5.25 V; DVCC = 2.7 V to 5.25 V; AGND = DGND = DAC_GND = 0 V; REF_IN = 2.5 V; OFFS_IN = 0 V; All outputs unloaded. All specifications TMIN to TMAX unless otherwise noted.)
Parameter1
DAC
Min
A Version2 Typ 14 0.1 0.5 +15 -0.3 2.5 0.001
Max
Unit Bits % of FSR LSB mV % of FSR V A V A ppm/C V V k pF mA dB dB V A V V V V mV pF V V V V mA mA mA mA mW
Conditions/Comments
DC PERFORMANCE Resolution Integral Nonlinearity (INL) Differential Nonlinearity (DNL) Offset Error Full-Scale Error
-0.39 -1 -10 -1 2.375
+0.39 +1 +50 +0.5 2.625 1 VDD - 1.5 1
See TPC 7 Monotonic See TPC 8 See TPC 9
VOLTAGE REFERENCE REF_IN Input Voltage Range3 Input Current ANALOG INPUT OFFS_IN Input Voltage Range3, 4 Input Current ANALOG OUTPUTS (VOUT0-VOUT31) Output Temperature Coefficient3, 5 DC Output Impedance3 Output Range4 OFFS_IN = 0 OFFS_IN = REF_IN Resistive Load3 Capacitive Load3 Short-Circuit Current3 DC Power-Supply Rejection Ratio3 DC Crosstalk3 DIGITAL INPUTS Input Current Input Low Voltage Input High Voltage Input Hysteresis (SCLK and SYNC Only) Input Capacitance POWER SUPPLY VOLTAGES VDD VSS AVCC DVCC POWER SUPPLY CURRENTS6 IDD ISS AICC DICC POWER DISSIPATION6
3
0 0.1 20 0.5
0 - 2REF_IN -REF_IN to +REF_IN 5 100 7 -70 -70 120 5 2.4 2.0 200 10 +4.75 -4.75 4.75 2.7 9 9 6.5 0.1 123 +12 -12 5.25 5.25 12 12 10 0.5 10 0.8 0.4
VDD = +10 V 5% VSS = -10 V 5%
DVCC = 5 V DVCC = 3 V DVCC = 5 V DVCC = 3 V
5% 10% 5% 10%
All Channels Full Scale All Channels Full Scale VIH = DVCC and VIL = DGND VDD = +5 V, VSS = -5 V
NOTES 1 See Terminology 2 A Version: Industrial temperature range -40C to +85C; typical at 25C. 3 Guaranteed by design and characterization, not production tested. 4 Output range is restricted from V SS + 2 V to V DD - 2 V. 5 AD780 as reference for the AD5532HS. 6 Outputs unloaded. Specifications subject to change without notice.
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AD5532HS
(VDD = +4.75 V to +12 V, VSS = -4.75 V to -12 V; AVCC = 4.75 V to 5.25 V; DVCC = 2.7 V to 5.25 V; AGND = DGND = DAC_GND = 0 V; REF_IN = 2.5 V; All outputs unloaded. All specifications TMIN to TMAX unless otherwise noted.)
Parameter1, 2 Output Voltage Settling Time Slew Rate Digital-to-Analog Glitch Impulse Digital Crosstalk Analog Crosstalk Digital Feedthrough Output Noise Spectral Density @ 1 kHz
4
AC CHARACTERISTICS
A Version3 10 0.85 1 5 1 0.2 170
Unit s max V/s typ nV-s typ nV-s typ nV-s typ nV-s typ nV/Hz typ
Conditions/Comments 100 pF, 5 k Load; Full-Scale Change 1 LSB Change around Major Carry
NOTES 1 See Terminology 2 Guaranteed by design and characterization, not production tested 3 B Version: Industrial temperature range -40C to +85C. 4 Timed from the end of a write sequence. Specifications subject to change without notice.
TIMING CHARACTERISTICS
Parameter1, 2, 3 fUPDATE fCLKIN t1 t2 t3 t4 t5 t6 t7 t8 t9
(VDD = +4.75 V to +12 V, VSS = -4.75 V to -12 V; AVCC = 4.75 V to 5.25 V; DVCC = 2.7 V to 5.25 V; AGND = DGND = DAC_GND = 0 V; All specifications TMIN to TMAX unless otherwise noted.)
Limit at TMIN, TMAX (A Version) 1.1 30 13 13 15 50 10 10 5 280 20 Unit MHz max MHz max ns min ns min ns min ns min ns min ns min ns min ns min ns min Conditions/Comments Channel Update Rate SCLK Frequency SCLK High Pulsewidth SCLK Low Pulsewidth SYNC Falling Edge to SCLK Falling Edge Setup Time SYNC Low Time SYNC High Time DIN Setup Time DIN Hold Time 19th SCLK Falling Edge to SYNC Falling Edge for Next Write RESET Pulsewidth
NOTES 1 See Timing Diagrams in Figure 1. 2 Guaranteed by design and characterization, not production tested. 3 All input signals are specified with t R = tF = 5 ns (10% to 90% of DV CC) and timed from a voltage level of (V IL + VIH)/2. Specifications subject to change without notice.
t1
SCLK 1 2 3 4 5 16 17 18 19 1
t3 t5
SYNC
t2
t4
t6 t7
t8
DIN MSB RESET LSB
t9
Figure 1. Serial Interface Timing Diagram
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AD5532HS
ABSOLUTE MAXIMUM RATINGS 1, 2
(TA = 25C unless otherwise noted)
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +17 V VSS to AGND . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to -17 V AVCC to AGND, DAC_GND . . . . . . . . . . . . . -0.3 V to +7 V DVCC to DGND . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +7 V Digital Inputs to DGND . . . . . . . . . . -0.3 V to DVCC + 0.3 V REF_IN to AGND, DAC_GND . . . . . . . . . . . -0.3 V to +7 V VOUT0-VOUT31 to AGND . . . . . . . VSS - 0.3 V to VDD + 0.3 V VOUT0-VOUT31 to VSS . . . . . . . . . . . . . . . . . . -0.3 V to +24 V OFFS_IN to AGND . . . . . . . . . . . VSS - 0.3 V to VDD + 0.3 V AGND to DGND . . . . . . . . . . . . . . . . . . . . . -0.3 V to +0.3 V Operating Temperature Range Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to +85C Storage Temperature Range . . . . . . . . . . . . -65C to +150C
Junction Temperature (TJ max) . . . . . . . . . . . . . . . . . . 150C 74-Lead LFBGA Package, JA Thermal Impedance . . . 41C/W Reflow Soldering Peak Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 220C Time at Peak Temperature . . . . . . . . . . . . 10 sec to 40 sec Max Power Dissipation at TA = 70C, Outputs Loaded . . . . . . . . . . . . . . . . . . . . . . . . . . 550 mW3 (for TA > 70C, derate at 26 mW for each C over 70C)
NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Transient currents of up to 100 mA will not cause SCR latch-up. 3 This limit includes load power and applies only when there is a resistive load on VOUT outputs.
ORDERING GUIDE
Model AD5532HSABC
Function 32 DACs
Output Voltage Span 5V
Package Description 74-Ball LFBGA
Package Option BC-74
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD5532HS features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
FULL-SCALE ERROR
OUTPUT VOLTAGE
ACTUAL IDEAL
OFFSET ERROR
0
DAC CODE
16k
Figure 2. DAC Transfer Function (OFFS_IN = 0)
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AD5532HS
PIN CONFIGURATION
1 2 3 4 5 6 7 8 9 10 11
A B C D E F G H J K L
A B C D E
TOP VIEW
F G H J K L
1
2
3
4
5
6
7
8
9
10
11
AD5532HS 74-Ball (LFBGA) Configuration
LFBGA Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 C1 C2 C6
Ball Name N/C N/C N/C N/C SYNC DVCC SCLK N/C N/C RESET N/C VO16 N/C N/C N/C N/C DGND DIN DGND N/C N/C REF_IN VO18 DAC_GND1 N/C
LFBGA Number C10 C11 D1 D2 D10 D11 E1 E2 E10 E11 F1 F2 F10 F11 G1 G2 G10 G11 H1 H2 H10 H11 J1 J2 J6
Ball Name AVCC1 N/C VO20 DAC_GND2 AVCC2 N/C VO26 VO14 AGND1 OFFS_IN VO25 VO21 AGND2 VO6 VO24 VO8 VO5 VO3 VO23 N/C VO4 VO7 VO22 VO19 VSS2
LFBGA Number J10 J11 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11
Ball Name VO9 VO11 VO17 VO15 VO27 VSS3 VSS1 VSS4 VDD2 VO2 VO10 VO13 VO12 N/C VO28 VO29 VO30 VDD3 VDD1 VDD4 VO31 VO0 VO1 N/C
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AD5532HS
PIN FUNCTION DESCRIPTIONS
Pin AGND (1-2) AVCC (1-2) VDD (1-4) VSS (1-4) DGND DVCC DAC_GND (1-2) REF_IN VOUT0-VOUT31 SYNC SCLK* DIN* OFFS_IN RESET*
Function Analog GND Pins. Analog Supply Pins. Voltage range from 4.75 V to 5.25 V. VDD Supply Pins. Voltage range from 8 V to 12 V. VSS Supply Pins. Voltage range from -4.75 V to -12 V. Digital GND Pins. Digital Supply Pins. Voltage range from 2.7 V to 5.25 V. Reference GND Supply for All the DACs. Reference Voltage for Channels 0-31. Analog Output Voltages from the 32 Channels. Active Low Input. This is the Frame Synchronization signal for the serial interface. While SYNC is low, data is transferred in on the falling edge of SCLK. Serial Clock Input. Data is clocked into the shift register on the falling edge of SCLK. This operates at clock speeds up to 30 MHz. Serial Data Input. Data must be valid on the falling edge of SCLK. Offset Input. The user can connect this to GND or REF_IN to determine the output span. Active Low Input. This pin can also be used to reset the complete device to its power-on-reset conditions.
*Internal pull-up device on this logic input. Therefore, it can be left floating and will default to a logic high condition.
TERMINOLOGY
Integral Nonlinearity (INL)
Output Voltage Settling Time
A measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is expressed as a percentage of full-scale range.
Differential Nonlinearity (DNL)
The time taken from when the last data bit is clocked into the DAC until the output has settled to within 0.5 LSB of its final value.
Digital-to-Analog Glitch Impulse
The difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified DNL of 1 LSB maximum ensures monotonicity.
Offset Error
The area of the glitch injected into the analog output when the code in the DAC register changes state. It is specified as the area of the glitch in nV-secs when the digital code is changed by 1 LSB at the major carry transition (011 . . . 11 to 100 . . . 00 or 100 . . . 00 to 011 . . . 11).
Digital Crosstalk
A measure of the error present at the device output with all 0s loaded to the DAC. It includes the offset of the DAC and the output amplifier. It is expressed in mV.
Full-Scale Error
The glitch impulse transferred to the output of one DAC at midscale while a full-scale code change (all 1s to all 0s and vice versa) is being written to another DAC. It is expressed in nV-secs.
Analog Crosstalk
A measure of the output error with all 1s loaded to the DAC. Ideally the output should be 2 REF_IN if OFFS_IN = 0. It is expressed as a percentage of full-scale range.
DC Power-Supply Rejection Ratio (PSRR)
The area of the glitch transferred to the output (VOUT) of one DAC due to a full-scale change in the output (VOUT) of another DAC. The area of the glitch is expressed in nV-secs.
Digital Feedthrough
A measure of the change in analog output for a change in supply voltage (VDD and VSS). It is expressed in dB. VDD and VSS are varied 5%.
DC Crosstalk
The dc change in the output level of one DAC at midscale in response to a full-scale code change (all 0s to all 1s and vice versa) and output change of all other DACs. It is expressed in V.
Output Temperature Coefficient
A measure of the impulse injected into the analog outputs from the digital control inputs when the part is not being written to, i.e., SYNC is high. It is specified in nV-secs and measured with a worst-case change on the digital input pins, e.g., from all 0s to all 1s and vice versa.
Output Noise Spectral Density
A measure of the change in analog output with changes in temperature. It is expressed in ppm/C.
A measure of internally generated random noise. Random noise is characterized as a spectral density (voltage per root Hertz). It is measured by loading all DACs to midscale and measuring noise at the output. It is measured in nV/Hz.
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Typical Performance Characteristics- AD5532HS
1.0 0.8 0.6 VREF_IN = 2.5V VOFFS_IN = 0V TA = 25 C 1.0 0.2
5.000 VREFIN = 2.5V VOFFS_IN = 0V DAC LOADED TO FULL SCALE
INL ERROR - % FSR
0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 0 2K 4K 6K 8K 10K 12K 14K16K DAC CODE
DNL ERROR - LSBs
DAC ERROR -LSBs
0.5 DNL MAX 0.0 INL MAX
0.1
4.995
VOUT - V
0.0
INL MIN -0.5 DNL MIN -1.0 -40 -0.2 0 40 TEMPERATURE - C 80 -0.1
4.990
4.985 -40
0 40 TEMPERATURE - C
80
TPC 1. Typical DNL Plot
TPC 2. INL Error and DNL Error vs. Temperature
TPC 3. VOUT vs. Temperature
2.535 TA = 25 C VREFIN = 2.5V VOFFS_IN = 0V DAC LOADED TO MIDSCALE 2.530
6 5 4
VOUT - V
2.520 2.518 2.516 2.514 2.512 2.510 2.508 2.506 2.504 2.502 TA = 25 C VREFIN = 2.5V VOFFS_IN = 0V
VOUT - V
3 2 1 0
2.525
TA = 25 C VREFIN = 2.5V VOFFS_IN = 0V
VOUT - V
2.500 2.498 2.496 2.494 TIME BASE - 200ns/DIV
2.520 6 2 0 -2 -4 4 SINK/SOURCE CURRENT - mA -6
-1 TIME BASE - 1.25 s/DIV
TPC 4. VOUT Source and Sink Capability
15
TPC 5. Full-Scale Settling Time
TPC 6. Major Code Transition Glitch Impulse
20
15
FREQUENCY - %
10
FREQUENCY - %
10
FREQUENCY - %
10
5
5
0 0 0.1 0.2 % FSR 0.3
0 0 10 mV 20 30
0 -1.0
-0.5 % FSR
0.0
TPC 7. INL Error Distribution at 25C
TPC 8. Offset Error Distribution at 25C
TPC 9. Full-Scale Error Distribution at 25C
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FUNCTIONAL DESCRIPTION Reset Function
The AD5532HS consists of 32 DACs in a single package. A 14-bit digital word is loaded into one of the 32 DAC registers via the serial interface. This is then converted (with gain and offset) into an analog output voltage (VOUT0-VOUT31). To update a DAC's output voltage, the required DAC is addressed via the serial port. When the 5-bit DAC address and 14-bit DAC data have been loaded the selected DAC converts the code. On power-on, all the DACs are loaded with zeros.
Digital-to-Analog Section
The reset function on the AD5532HS can be used to reset all nodes on the device to their power-on-reset condition. All the DACs are loaded with 0s and all registers are cleared. The reset function is implemented by taking the RESET pin low.
SERIAL INTERFACE
The serial interface is controlled by three pins as follows: SYNC: This pin is the Frame Synchronization pin for the serial interface. SCLK: This pin is the Serial Clock Input. It operates at clock speeds up to 30 MHz. DIN: This pin is the Serial Data Input. Data must be valid on the falling edge of SCLK. To update a single DAC channel a 19-bit data-word is written into the AD5532HS. See Table II.
Table II. Serial Data Format
The architecture of each DAC channel consists of a resistorstring DAC followed by an output buffer amplifier. The voltage at the REF_IN pin provides the reference voltage for the corresponding DAC. Since the input coding to the DAC is straight binary, the ideal DAC output voltage is given by:
VREF _ IN x D 214 where D = decimal equivalent of the binary code that is loaded to the DAC register i.e., 0-16,383. VDAC =
Output Buffer Stage--Gain and Offset
MSB A4 A3 A2 A1 A0
LSB DB13-DB0
The function of the output buffer stage is to translate the 0 V-2.5 V output of the DAC to a wider range. This is done by gaining up the DAC output by two and offsetting the voltage by the voltage on OFFS_IN pin. VOUT = (2 x VDAC ) - VOFFS _ IN VDAC is the output of the DAC. VOFFS_IN is the voltage at the OFFS_IN pin. Table I shows how the output range of VOUT relates to the offset voltage supplied by the user.
Table I. Sample Output Voltage Ranges
A4-A0 Bits
Used to address any one of the 32 channels (A4 = MSB of address, A0 = LSB).
DB13-DB0 Bits
These are used to write a 14-bit word into the addressed DAC register. Figure 1 shows the timing diagram for a serial write to the AD5532HS. The serial interface works with both a continuous and a noncontinuous serial clock. The first falling edge of SYNC resets a counter that counts the number of serial clocks to ensure the correct number of bits are shifted in and out of the serial shift registers. Any further edges on SYNC are ignored until the correct number of bits are shifted in or out. Once 19 bits have been shifted in or out, the SCLK is ignored. In order for another serial transfer to take place, the counter must be reset by the falling edge of SYNC. The user must allow 280 ns (min) between successive writes (refer to Timing Specifications).
VOFFS_IN (V) 0 2.5
VDAC (V) 0 to 2.5 0 to 2.5
VOUT (V) 0 to 5 -2.5 to +2.5
VOUT is limited only by the headroom of the output amplifiers. VOUT must be within maximum ratings.
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MICROPROCESSOR INTERFACING AD5532HS-to-ADSP-21xx Interface AD5532HS-to-PIC16C6x/7x Interface
The ADSP-21xx family of DSPs are easily interfaced to the AD5532HS without the need for extra logic. A data transfer is initiated by writing a word to the Tx register after the SPORT has been enabled. In a write sequence, data is clocked out on each rising edge of the DSP's serial clock and clocked into the AD5532HS on the falling edge of its SCLK. The easiest way to provide the 19-bit data-word required by the AD5532HS, is to transmit two 10-bit data-words from the ADSP-21xx. Ensure that the data is positioned correctly in the TX register so that the first 19 bits transmitted contain valid data. The SPORT control register should be set up as follows: TFSW = 1, Alternate Framing INVTFS = 1, Active Low Frame Signal DTYPE = 00, Right Justify Data ISCLK = 1, Internal Serial Clock TFSR = 1, Frame Every Word ITFS = 1, Internal Framing Signal SLEN = 1001, 10-Bit Data Word Figure 3 shows the connection diagram.
The PIC16C6x/7x Synchronous Serial Port (SSP) is configured as an SPI Master with the Clock Polarity bit = 0. This is done by writing to the Synchronous Serial Port Control Register (SSPCON). See user PIC16/17 Microcontroller User Manual. In this example I/O port RA1 is being used to pulse SYNC and enable the serial port of the AD5532HS. This microcontroller transfers only eight bits of data during each serial transfer operation; therefore, three consecutive write operations are necessary to transmit 19 bits of data. Data is transmitted MSB first. It is important to left-justify the data in the SPDR register so that the first 19 bits transmitted contain valid data. RA1 must be pulled low to start a transfer. It is taken high and pulled low again before any further write cycles can take place. Figure 5 shows the connection diagram.
AD5532HS*
SCLK DIN SYNC PIC16C6x/7x* SCK/RC3 SDI/RC4 RA1
*ADDITIONAL PINS OMITTED FOR CLARITY
AD5532HS*
SCLK DIN SYNC
ADSP-2101/ ADSP-2103* SCLK DT TFS
Figure 5. AD5532HS-to-PIC16C6x/7x Interface
AD5532HS-to-8051 Interface
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 3. AD5532HS-to-ADSP-2101/ADSP-2103 Interface
AD5532HS-to-MC68HC11 Interface
The Serial Peripheral Interface (SPI) on the MC68HC11 is configured for Master Mode (MSTR = 1), Clock Polarity Bit (CPOL) = 0 and the Clock Phase Bit (CPHA) = 1. The SPI is configured by writing to the SPI Control Register (SPCR)--see 68HC11 User Manual. SCK of the 68HC11 drives the SCLK of the AD5532HS and the MOSI output drives the serial data line (DIN) of the AD5532HS. The SYNC signal is derived from a port line (PC7). When data is being transmitted to the AD5532HS, the SYNC line is taken low (PC7). Data appearing on the MOSI output is valid on the falling edge of SCK. The 68HC11 transfers only eight bits of data during each serial transfer operation; therefore, three consecutive write operations are necessary to transmit 19 bits of data. Data is transmitted MSB first. It is important to left-justify the data in the SPDR register so that the first 19 bits transmitted contain valid data. PC7 must be pulled low to start a transfer. It is taken high and pulled low again before any further write cycles can take place. See Figure 4.
AD5532HS*
SCLK DIN SYNC SCK MOSI PC7 MC68HC11*
The AD5532HS requires a clock synchronized to the serial data. The 8051 serial interface must therefore be operated in Mode 0. In this mode serial data exits the 8051 through RxD and a shift clock is output on TxD. The SYNC signal is derived from a port line (P1.1). Figure 6 shows how the 8051 is connected to the AD5532HS. Because the AD5532HS shifts data out on the rising edge of the shift clock and latches data in on the falling edge, the shift clock must be inverted. Note also that the AD5532HS requires its data with the MSB first. Since the 8051 outputs the LSB first, the transmit routine must take this into account.
AD5532HS*
SCLK DIN SYNC TxD RxD P1.1 8051*
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 6. AD5532HS-to-8051 Interface
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 4. AD5532HS-to-MC68HC11 Interface
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APPLICATION CIRCUITS AD5532HS in an Optical Network Control Loop
The AD5532HS can be used in optical network applications that require a large number of DACs to perform a control and measurement function. In the circuit shown in Figure 7, the 0 V-5 V outputs of the AD5532HS are amplified to a range of 0 V-180 V and then used to control actuators that determine the position of MEMS mirrors in an optical switch. The exact position of each mirror is measured using sensors. The sensor readings are muxed using four dual 4-channel matrix switches (ADG739) and fed back to an 8-channel 14-bit ADC (AD7856). The control loop is driven by an ADSP-21065L, a 32-bit SHARC(R) DSP with an SPI-compatible SPORT interface. It writes data to the DAC, controls the multiplexor, and reads data from the ADC via a 3-wire serial interface.
S 1E 1 ACTUATORS N ADG739 AD5532HS 0V-180V FOR MEMS S 4 AMPS MIRROR O ARRAY 32 32 R S
DAC DAC DAC STORED DATA AND INHIBIT PATTERN FORMATTER DAC PERIOD GENERATION AND DELAY TIMING ACTIVE LOAD
PARAMETRIC MEASUREMENT SYSTEM BUS UNIT
DRIVER DAC
DUT
DAC COMPARE REGISTER DAC
DACs 1 AD7856 8
SYSTEM BUS
COMPARATOR
Figure 9. AD5532HS in an ATE System
POWER SUPPLY DECOUPLING
ADSP-21065L
Figure 7. AD5532HS and DSP Control an Optical Switch
Alternatively, the AD5532HS can be driven by an ADMC401 Motor-Controller as shown in the control-loop in Figure 8. The DAC outputs are fed into eight AD8534 quad transconductance amps to generate currents for voice-coil actuators that determine the position of the mirrors. The exact position of each mirror is measured and the readings are muxed into the on-chip 8-channel ADC of the ADMC401.
S VOICE-COIL 1 E N ACTUATORS S ADG704 FOR 8 O MEMS 32 R MIRROR S ARRAY
1
1
AD5532HS
32 AD8534 8
8 AD8544 2
In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. The printed circuit board on which the AD5532HS is mounted should be designed so that the analog and digital sections are separated, and confined to certain areas of the board. If the AD5532HS is in a system where multiple devices require an AGND-to-DGND connection, the connection should be made at one point only. The star ground point should be established as close as possible to the device. For supplies with multiple pins (VSS, VDD, AVCC), it is recommended to tie those pins together. The AD5532HS should have ample supply bypassing of 10 F in parallel with 0.1 F on each supply located as close to the package as possible, ideally right up against the device. The 10 F capacitors are the tantalum bead type. The 0.1 F capacitor should have low Effective Series Resistance (ESR) and Effective Series Inductance (ESI), like the common ceramic types that provide a low impedance path to ground at high frequencies, to handle transient currents due to internal logic switching. The power supply lines of the AD5532HS should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other parts of the board, and should never be run near the reference inputs. A ground line routed between the DIN and SCLK lines will help reduce crosstalk between them (not required on a multilayer board as there will be a separate ground plane, but separating the lines will help). It is essential to minimize noise on REF_IN. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This reduces the effects of feedthrough through the board. A microstrip technique is by far the best, but not always possible with a doublesided board. In this technique, the component side of the board is dedicated to ground plane while signal traces are placed on the solder side. As is the case for all thin packages, care must be taken to avoid flexing the package and to avoid a point load on the surface of the package during the assembly process.
3
S P O R T
3
ADMC401
8-CH 12-BIT ADC
1 8
Figure 8. AD5532HS and ADMC401 Control an Optical Switch
AD5532HS in a Typical ATE System
The AD5532HS is ideally suited for use in Automatic Test Equipment. Several DACs are required to control pin drivers, comparators, active loads, and signal timing. Traditionally, sample-and-hold devices were used in this application. The AD5532HS has several advantages: no refreshing is required, there is no droop, pedestal error is eliminated, and there is no need for extra filtering to remove glitches. A higher level of integration is achieved in a smaller area (see Figure 9).
SHARC is a registered trademark of Analog Devices, Inc.
-10-
REV. 0
AD5532HS
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
74-Ball LFBGA (BC-74)
0.472 (12.00) BSC 0.394 (10.00) BSC
11 10 9 8 7 6 5 4 3 2 1
A1
TOP VIEW
0.472 (12.00) BSC
0.039 (1.00) BSC
BOTTOM VIEW
A B C D E 0.394 F (10.00) G BSC H J K L
DETAIL A 0.067 (1.70) MAX 0.020 (0.50) MIN
0.039 (1.00) BSC
DETAIL A
0.033 (0.85) MIN 0.024 (0.60) BSC BALL DIAMETER SEATING PLANE
CONTROLLING DIMENSIONS ARE IN MILLIMETERS
REV. 0
-11-
-12-
C02548-1.5-6/01(0)
PRINTED IN U.S.A.

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